Understanding the
Semiconductor Industry

The mental model

Scale. A modern transistor's smallest features sit between the size of an atom and the size of a living cell. A silicon atom is ~0.2 nanometers (nm) across; a red blood cell is ~7,000 nm. Transistors live in that gap.

Node names are marketing, not measurements. "3nm," "2nm," "18A" (= 1.8nm-class) are generational labels. No physical feature on a "3nm" chip is actually 3nm. Treat them as version numbers, not rulers.

Moore's Law — the observation that transistor density roughly doubles every ~2 years — is now slowing as physics hits limits. The industry compensates with advanced packaging (stacking and stitching multiple chips together) rather than pure shrinkage. (Chip War background)

The value chain — and where it narrows to a chokepoint

Chips flow through roughly seven stages. The danger isn't any single stage; it's that most stages are controlled by a tiny number of firms.

The single most important chokepoint is ASML of the Netherlands, the only company on Earth that makes EUV (extreme ultraviolet) lithography machines — the tools required for the most advanced chips. Each machine costs ~$150–380M+. This is the technical reason China cannot reach the leading edge. (ASML on EUV)

How a wafer is born: quartz sand → purified to polysilicon → grown into a single crystal ingot (the Czochralski method) → sliced into mirror-polished wafers → sent to a fab where hundreds of layers are patterned by lithography.

TSMC: the company the world runs on

Taiwan Semiconductor Manufacturing Company (TSMC, 台積電) is the most important manufacturer on the planet. Its lead is widening, not narrowing — foundry share rose from 62.8% (Q1 2024) to 72.3% (Q1 2026) while Samsung slipped to 6.5%.

• >90% of leading-edge production. At advanced nodes (7nm and below), TSMC controls over 90% of the market, with Samsung and Intel distant competitors.
• ~60–70% of all foundry revenue (72.3% in Q1 2026 per TrendForce). TSMC controls the majority of global foundry revenue.
• Cutting-edge concentration. 3nm and 5nm now drive 61% of revenue; HPC's share doubled from 30% (Q1 2020) to 61% (Q1 2026), driven by AI.
• Pricing power. Q1 2026 gross margin ~66%. When Nvidia, Apple, or AMD need their best chips, TSMC is effectively the only option.

Why it matters: roughly 90%+ of the world's most advanced chips are made on a single island that sits at the center of a geopolitical fault line. This is the "Silicon Shield" / Taiwan-risk thesis at the heart of Chip War.

Primary source: TSMC Q1 2026 SEC Form 6-K.

The economics of consolidation

This is the deepest idea in the industry. Moore's Law is as much an economic force as a technical one.

• Each new node's fab gets exponentially more expensive — a leading-edge fab now costs $20–40B+.
• Only the firm with the most volume can amortize that R&D and capex.
• That lets it invest more → widen its lead → win more volume. A winner-take-most flywheel.
• Result: the leading edge has collapsed from ~20+ companies in the 1990s to 3 today (TSMC, Samsung, Intel) — and really only one that is fully competitive.

Memory follows the same logic: a separate oligopoly of three (Samsung, SK Hynix, Micron).

The players, by region

Different regions own different chokepoints. No single country controls the whole chain — which is exactly why export controls bite and why the supply chain is a geopolitical instrument.

Europe (ex-NL) — Siltronic (wafers, Germany), Infineon, STMicroelectronics, Bosch — strong in automotive/industrial/power chips, not leading-edge logic.

Japan in depth — the quiet chokehold, and a 2nm comeback

Japan lost the chip manufacturing crown decades ago — its most advanced domestic node is still ~40nm — but it never lost the materials and equipment layer beneath everyone else's fabs. It holds a >50% share of 14 of the most critical chipmaking inputs, and is now spending ~0.71% of GDP (~$25.7B) to re-enter the frontier itself.

Korea in depth — the memory superpower, and an emerging #2 foundry

Korea's two giants make it the one country that could rival Taiwan's leverage — through memory rather than logic. AI has turned that into a windfall: Samsung and SK Hynix's combined Q2'26 operating profit was estimated near $98B, a record.

The catch for Korea: Samsung's foundry is still a distant #2 (~6.5% vs TSMC's 72%), and its HBM4 comeback hinges on qualification yields, not just added capacity. But for the first time in years both Korean giants are winning at the AI frontier — SK Hynix in memory, Samsung clawing back leading-edge logic.

Intel: the West's comeback bet

Intel lost its process leadership to TSMC around 2018–2020. Its entire recovery rests on the 18A node (1.8nm-class) and its foundry business winning outside customers.

• The win: Panther Lake launched at CES 2026 and began shipping Jan 27 — the first Intel chips built entirely on 18A, in high-volume manufacturing at Fab 52, Arizona.
• The tech: 18A introduces RibbonFET (gate-all-around) and PowerVia (backside power). Intel is first-to-market on backside power, though TSMC's N2 still beats it on density.
• The catch: yields remain below profitable levels and won't hit target cost thresholds until end of 2026 at the earliest.
• The real test: the 14A node, where external customers (reportedly including Apple in qualification) decide in H2 2026 whether Intel Foundry becomes viable. ("The Last Chance")

HBM: the second oligopoly & the inference memory-wall

High-Bandwidth Memory (HBM) is 3D-stacked DRAM that sits next to an AI GPU. Because AI workloads are memory-bandwidth-bound, HBM is as essential as the GPU itself. The market is a tight three-way race:

• Sold out well into the future. HBM3E and HBM4 are both fully booked through calendar 2027, with demand into 2028; the market is projected to reach ~$100B by 2028, up from ~$35B in 2025 — and after WSTS's June revision put total memory at $804B for 2026 (price surges across DRAM/NAND, not just HBM), that HBM figure looks conservative.
• Pricing spiral. HBM3 ~$200/stack, HBM3E ~$300, HBM4 ~$500.
• The HBM4 battle. Nvidia's Vera Rubin ships H2 2026 with HBM4; SK Hynix holds ~60–70% of the allocation. HBM supply is the gating constraint on Rubin volume.
• Micron's blowout confirms the supercycle (see chart below).
• Routes back to TSMC. HBM4's base logic die is now made by TSMC — even memory deepens the single point of dependency. (SK Hynix 2026 outlook)

Why HBM is the inference bottleneck (not FLOPs). Training is compute-bound; inference is memory-bound. During decode, the model generates one token at a time and must reload the KV cache (the stored keys/values for every prior token) from HBM on every single step — and HBM bandwidth, not compute, is what caps throughput. Adding more GPUs doesn't fix a memory-bound workload. Agentic workloads make this dramatically worse: an agent appends its reasoning, tool calls, and observations across dozens or hundreds of turns (coding-agent traces average ~157 rounds), so the KV-cache footprint grows monotonically over the agent's lifetime — turning memory from a short-lived optimization into the dominant system resource. The shift to agents is, underneath, a shift into a memory crunch. HBM is also 50%+ of a packaged GPU's cost.

China's legacy strategy

Blocked below ~7nm, China pivoted to dominating the mature/legacy market — chips at 28nm and above that run cars, appliances, and industrial gear. Larger feature sizes, commodity products, enormous volume.

• The flood. Blocked below 14nm by U.S. sanctions, China is flooding nodes above 28nm with state subsidies.
• Self-sufficiency goal. Chinese firms hold ~27% of 28–65nm production; by 2030, domestic capacity could cover ~90% of domestic demand, up from ~37% in 2020.
• The overcapacity problem. Mature-node utilization dropped to ~70% in 2024, triggering a U.S. Section 301 investigation into "dumping."
• Advanced grind. SMIC is doubling 7nm capacity and piloting 5nm for Huawei using older DUV tools — but Ascend 910C yields are reportedly 20–40%. Engineering grit at poor economics.

Balanced read: Analysts disagree on whether this is "overcapacity" in the threatening sense. CSIS argues mature chips are commodities driven mainly by domestic demand and import-substitution, not an export-dumping play like solar or EVs — so the framing matters.

China's champions: Huawei, SMIC & CXMT

Beyond the legacy flood, China is building a full roster of national champions to escape the chokepoints above. The pattern repeats: strong and rising in commodity tiers, years behind at the AI-critical frontier, and gated by the same EUV, equipment, memory, and photoresist controls.

Huawei (华为) — the demand-and-design anchor

Huawei's HiSilicon designs the Ascend (昇腾) accelerators that anchor China's entire domestic AI stack. The current Ascend 910C is a dual-die chip on SMIC's 7nm (N+2) DUV process — ~53B transistors, ~800 TFLOPS FP16, roughly 60–80% of an Nvidia H100 (a 2022 chip), paired with 128GB HBM. Being a node behind, Huawei's answer is to gang chips together at the system level:

• The roadmap climbs by architecture, not shrink. The 910D (5nm-class aspiration, HBM3e, ~1.2 PFLOPS) and 950PR (~1.56 PFLOPS FP4, still SMIC 7nm) squeeze more from the same node. Huawei's 2028 target is 4 ZettaFLOPS at system scale — not single-chip parity with Nvidia.
• The sanctions backstory. Teardowns found nearly every 910B/910C used TSMC 7nm dies, obtained via the shell company Sophgo (~2.9M dies; TSMC was fined $1B). That "die bank" carried Huawei through 2024–25 and is now effectively exhausted — 2026 output is fully domestic.

The real ceiling: HBM, not logic

Here is the counterintuitive part. SMIC can already make enough 7nm die for well over a million Ascends a year — but domestic HBM can't keep up. China stockpiled ~13M HBM stacks (mostly Samsung) before controls tightened; CXMT can produce only ~2M stacks in 2026 — enough for ~250,000–300,000 Ascend packages. The bottleneck has moved from the fab to the memory.

SMIC (中芯国际) — the grinding foundry

• Record year, thin margins. SMIC posted a record ~$9.3B in 2025 revenue; Q1'26 was ~$2.5B at ~20% gross margin, China ~88–90% of sales. Ironically, the AI boom is pulling mature-node orders back to Chinese foundries as global rivals chase HBM — Q2'26 revenue is guided up ~14–16%.
• Capacity & nodes. ~1.06M wafers/month (8-inch-equivalent), 12-inch capacity still expanding; 7nm capacity roughly doubling in 2026 and piloting 5nm — all on DUV, at reported 20–40% yields. Underwritten by the ~$47.5B "Big Fund III" (大基金三期).
• The ceiling is EUV. Without it, cost-per-wafer and yield stay structurally worse, and 3nm-class is simply out of reach.

CXMT (长鑫存储) & the rest of the roster

CXMT — ChangXin Memory Technologies (长鑫存储) is the DRAM champion and the one to watch: ~8% of global DRAM in 2026 (up from ~3%), now the #4 maker, DDR5 already in Lenovo laptops. But its DDR5 die runs ~40% larger than Samsung's and it's ~3–4 years behind on HBM — current profits reflect a hot market, not product superiority. The rest of the roster: YMTC (长江存储) in NAND; Hua Hong (华虹) in mature logic; and tool makers Naura (北方华创) & AMEC (中微) racing to replace Western equipment. No domestic EUV; DUV is the ceiling.

The throughline: China can increasingly self-supply the commodity layer and is a genuine pricing threat there. It stays structurally locked out of the frontier — and the binding constraint on its AI ambitions has now moved from logic (SMIC can build the dies) to memory (CXMT can't yet build the HBM).

Advanced packaging — the new bottleneck

Packaging used to be the boring back-end (putting a chip in plastic). Advanced packaging is now a frontier technology and the actual constraint on AI GPU supply.

• Because transistor shrink is slowing, performance gains now come from stitching multiple chips together — vertical die stacking, shared silicon interposers, "chiplets." TSMC's flagship method is CoWoS (Chip-on-Wafer-on-Substrate).
• Every Nvidia AI GPU needs CoWoS packaging, and CoWoS capacity — not chip fabrication — has been the binding limit.
• When people say "we can't get enough Blackwells," they usually mean the packaging line is full, not the transistor fab. A chokepoint sitting on top of a chokepoint.

The product that ties it together: Nvidia Vera Rubin

If you want one object that embodies every chokepoint in this brief, it's Nvidia's newest platform. "Vera Rubin" is not one chip — it's a six-chip platform (named after the astronomer who confirmed dark matter): Vera, Nvidia's second custom Arm CPU (88 "Olympus" cores, succeeding Grace), and Rubin, the GPU succeeding Blackwell, plus NVLink-6 switch, BlueField-4, CX-9 networking and the CPX variant. They ship as a rack-scale system, the VR200 NVL72.

Naming logic worth locking in: Grace + Blackwell → GB200 / GB300 (the "B300" is the Blackwell Ultra GPU — the 2025 mid-cycle refresh that still carries today's volume, on HBM3E). Vera + Rubin → VR200 — the new platform, on HBM4, ramping H2 2026.

Why it's the whole brief in one product:

• Fab chokepoint → TSMC 3nm. Packaging chokepoint → CoWoS-L. Memory chokepoint → HBM4 is the gating constraint on how many Rubins can ship.
• The power wall, made physical. A VR200 rack draws ~190–230 kW vs ~120–130 kW for Blackwell; Rubin Ultra "Kyber" is spec'd at ~600 kW, with 1 MW-class racks behind it — forcing an 800 VDC, all-liquid-cooling redesign.
• The memory-wall, designed around. Rubin splits the workload — standard Rubin GPUs (HBM4) handle bandwidth-bound decode, while a GDDR7-based Rubin CPX handles compute-bound long-context prefill.
• Nvidia even announced a Space-1 Vera Rubin Module for orbital data centers — the clearest signal yet that power/siting constraints are pushing compute to extremes.

Cadence: Blackwell (2024) → Blackwell Ultra/B300 (2025) → Rubin (2026) → Rubin Ultra "Kyber" (2027) → Feynman (2028). Specs verified at CES/GTC 2026.

The demand layer: AI capex & the power wall

The AI buildout has rewritten the demand side of the entire industry. The right metric for data centers is IT load in megawatts (MW) / gigawatts (GW), not square footage — power measures actual compute capacity.

• The Gigawatt Era. The industry has moved from the "Megawatt Era" to the "Gigawatt Era," where AI data centers consume as much power as major cities.
• Capex is vertical. The six largest US hyperscalers are on track for ~$700B in 2026 capex, rising to ~$820B in 2027. Goldman frames the decade-long buildout at ~$7.6 trillion.
• Capital intensity is utility-like. Hyperscalers now spend 45–57% of revenue on capex — funded increasingly by debt.

Power is now the binding constraint — not chips, not money. The defining 2026 scenario is a split by access to power: sites with secured grid connections boom; a large share of announced capacity stalls in interconnection queues. (Morgan Stanley: the AI power bottleneck)

The geopolitical layer

• Export controls. The US restricts China's access to EUV machines, advanced GPUs, EDA software, and certain manufacturing equipment — the structural reason China is stuck at the leading edge.
• Taiwan concentration risk. ~90%+ of advanced chips made on one island. Diversification (Arizona, Japan, Germany) is real but partial and years from changing the dependency.
• Trade friction. China's mature-node expansion has triggered US/EU investigations; a mature-node market-share reversal vs. Taiwan is projected by some analysts around 2027.

Outlook: 2 / 5 / 10 years

Predictions — dated and falsifiable

Forecasts are cheap; dated, checkable calls are not. Six, with confidence levels, written 2026-07.

Areas to explore deeper

Where this report stops and the next layer of edge begins — each one is a standalone research thread with real money attached.

• Custom HBM and the memory/logic blur. HBM4E/HBM5 base dies are going custom — Samsung is using 2nm logic for base dies and hired ~250 engineers for custom projects targeting Google, Meta and Nvidia. When memory ships with customer-specific logic inside, who captures the margin: the memory maker, the foundry, or the customer? This is the next re-rating fight.
• Disaggregated inference economics (Rubin CPX). The prefill/decode split reprices inference: GDDR7 compute for long-context prefill at a fraction of HBM cost. Model the cost-per-token curves — this determines GPU-cloud pricing power over the next two years and which operators' fleets are best positioned.
• The power-procurement market. 4+ year grid queues have created a shadow market in energized capacity: behind-the-meter gas, SMR pre-orders, nuclear restarts, and "powered land" as an asset class. Distributed and edge GPU capacity partially sidesteps single-site power walls — worth mapping who benefits.
• China's HBM shadow supply chain. The ~13M-stack stockpile, its depletion curve, third-party leakage routes (the Samsung HBM found in new Ascends), and CXMT's real HBM3 timeline. This single variable sets China's 2027–28 AI compute ceiling.
• Packaging after CoWoS. Panel-level packaging, glass substrates (JEDEC just approved the SPHBM4 standard), and hybrid bonding are the next capacity race — whoever breaks the interposer constraint resets AI GPU supply math.
• The consumer backlash & regulatory risk. Memory at ~35% of PC BOM, +17% PC prices, and the Garciaguirre v. Samsung price-fixing class action (Jun 2026). A supercycle that visibly taxes consumers invites political intervention — the tail risk nobody is pricing.
• The sanctions paradox on mature nodes. AI is pulling global orders back to SMIC and Hua Hong as Western foundries pivot to advanced/AI — Q2'26 SMIC guided +14–16%. Track whether export policy shifts from blocking China's frontier to also defending the legacy floor (Section 301 outcome).

Glossary

Node (e.g. 3nm, 18A)

A chip generation label — a version number, not a physical measurement.

Fab

Fabrication plant where chips are made. Leading-edge fabs cost $20–40B+.

Foundry

A fab that manufactures chips for other companies (the "fabless" designers).

EUV

Extreme ultraviolet lithography — the ASML-monopoly tech for printing the most advanced circuits.

Wafer

The blank polished silicon disc that chips are built on.

HBM

High-bandwidth memory — 3D-stacked DRAM beside an AI GPU.

DRAM / NAND

The two big memory types — DRAM is fast working memory (HBM is a stacked DRAM variant); NAND is flash storage.

KV cache

The stored keys/values for every prior token, reloaded from HBM on each decode step — the reason inference is memory-bound and agents blow up memory use.

Vera Rubin (VR200)

Nvidia's next platform (2026) — Vera CPU + Rubin GPU, on HBM4. Succeeds Grace+Blackwell (GB200/GB300).

CoWoS

TSMC's advanced packaging method; the binding constraint on AI GPU supply.

Chiplet

A small chip combined with others into one package instead of one large monolithic die.

RibbonFET / gate-all-around (GAA)

The newest transistor architecture, succeeding FinFET.

PowerVia / backside power delivery

Routing power under the wafer to improve efficiency.

Fabless

A company that designs chips but outsources manufacturing (e.g. Nvidia, Apple).

OSAT

Outsourced assembly and test — the packaging/test specialists (ASE, Amkor).

EDA

Electronic design automation — the software chips are designed in.

Hyperscaler

A massive cloud/data-center operator (Amazon, Microsoft, Google, Meta).

IT load (MW/GW)

The power delivered to computing equipment; the true measure of data-center scale.